1. Field of the Invention
The present invention relates to a high voltage generation circuit, and more particularly to, a high voltage generation circuit capable of improving a yield by controlling a defect due to a write recovery time tWR margin shortage, by generating a first high voltage during an active operation and generating a second high voltage higher than the first high voltage, in sequence, during a precharging operation.
2. Discussion of Related Art
Dynamic Random Access Memory DRAM is a volatile memory device storing data in a cell comprised of a transistor and a capacitor. In order to read and write data in the DRAM cell, a high voltage Vpp higher than an external supply voltage Vcc is generated and applied to a cell word line. As a result, a cell transistor is turned on/off. However, when the high voltage is too high, it has a bad influence to reliability of the cell transistor. Accordingly, the DRAM device has used a voltage a little bit higher than a voltage that adds the external supply voltage Vcc and a threshold voltage Vt of the cell transistor.
The high voltage is generated by using a high voltage generation circuit as shown in FIG. 1. The high voltage generation circuit is basically comprised of an oscillator 11, a pumping circuit 12, and a level detection circuit 13. The oscillator is operated by an enable signal EN, generating an oscillation signal OSC with a constant period. The pumping circuit 12 generates a high voltage Vpp by a pumping operation using an external supply voltage Vcc in response to the oscillation signal OSC. Furthermore, the level detection circuit 13 detects whether or not the high voltage is risen to a target value by comparing a reference voltage and the high voltage Vpp, and according to the result, the level detection circuit 13 controls the operation of the oscillator 11 and maintains a constant potential of the high voltage.
However, as a design rule is getting smaller, the sizes of a a storage node contact and a bitline contact of a cell transistor are getting smaller as well. As a result, as cell threshold voltages have different values according to a manufacturing process, and thus there are many cells which can't transfer data of the bitline to a cell capacitor within a constant time, a yield of the device is decreased thereto. Especially, during a data write operation, a defect by a write recovery time tWR margin shortage, as a time fixed for storing data in the cell capacitor before precharing operation, is becoming a serious problem these days when the manufacturing process is getting sub-micron design-rule.